1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which is electrically writable, readable, and erasable, and a manufacturing method thereof. More specifically, the present invention relates to the structure of a floating gate in the nonvolatile semiconductor memory device.
2. Description of the Related Art
Nonvolatile memory to which data can be electrically rewritten and stored even with the power turned off has expanded in the marketplace. Features of a nonvolatile memory lie in that its structure is similar to that of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a region capable of accumulating (storing) electric charge for a long period of time is provided over a channel forming region. This electric charge accumulation region is formed over an insulating layer and also referred to as a floating gate due to being insulated from the surrounding area. A control gate is further provided over the floating gate with an insulating layer interposed between the control gate and the floating gate.
Operations in which electric charge is stored in the floating gate and then released by application of a voltage to the control gate are performed in a so-called floating gate type of nonvolatile memory that has such a structure. That is, in the structure, data is stored through transfer of charge into and out of the floating gate. Specifically, injection and release of electric charge to and from the floating gate is performed by application of a high voltage between the semiconductor layer forming the channel formation region and the control gate. At this time, it is said that a Fowler-Nordheim type (F-N type) of tunneling current (NAND type) or thermoelectrons (NOR type) flow in the insulating layer formed over the channel formation region. Because of this, the insulating layer is also called a tunneling insulating layer.
As for a floating-gate type of nonvolatile memory, in order that reliability be guaranteed, a property through which charge can be stored in the floating gate for ten years or more is required. For that purpose, in the tunneling insulating layer, with the tunneling insulating layer being formed at a thickness at which tunneling current can flow, a high insulating property is required so that charge does not leak.
In addition, the floating gate formed over the tunneling insulating layer is formed of silicon, the same semiconductor material of which the semiconductor layer forming the channel formation region is formed. Specifically, a method of forming the floating gate of polycrystalline silicon has expanded; for example, a floating gate formed of a polycrystalline silicon film deposited at a thickness of 400 nm is known (refer to Patent Document 1: Japanese Published Patent Application No. 2000-58685 (Page 7, FIG. 7).